Due to their relatively simple implementation and low cost in the application of intermediate speed and resolution, Pipelined Algorithmic Analog-to-Digital Converters (ADC) are found in various applications, including image sensors, communication and television. A component found at each stage of a Pipelined Algorithmic ADC is an operational amplifier (OP-AMP). The majority of the power consumption of a pipeline ADC is in the OP-AMPs, so OP-AMP sharing is desirable to minimize the number of OP-AMPs used. However, without the use of a reset phase in an OP-AMP sharing structure to eliminate residual signals from prior phases, amplification during a phase may be affected by a residue from a prior phase stored in capacitances of the OP-AMP input pair. This problem becomes more pronounced when a large or full-swing input signal exists, for example, when an image sensor pixel is exposed to bright light, resulting in a white pixel, that may either be converted improperly or may affect conversion of a following pixel. This is an example of a phenomenon known as the memory effect.
One method to reduce the occurrence of the memory effect in Pipeline ADCs is to insert a charge-reset phase between clock cycles. However, this has the effect of reducing the clock speed of the Pipeline ADC.